ARC detection approach

ABSTRACT

An apparatus and technique are provided for generating a plasma using a power supply circuit and arc detection arrangement. The power supply circuit has a cathode enclosed in a chamber, and is adapted to generate a power-related parameter. The arc detection arrangement is communicatively coupled to the power supply circuit and adapted to assess the severity of arcing in the chamber by comparing the power-related parameter to at least one threshold. According to various implementations, arc occurrences, arcing duration, intensity and/or energy are measured responsive to comparing the power-related parameter to the at least one threshold. According to further implementations, the above-mentioned measured quantities are accumulated and/or further processed.

RELATED PATENT DOCUMENTS

[0001] This is a continuation of U.S. patent application Ser. No.10/121,445, entitled “Apparatus and Method for ARC Detection” and filedon Apr. 12, 2002, to which priority is claimed under 35 U.S.C. §120.

FIELD OF THE INVENTION

[0002] The present invention is directed to arc detection and, moreparticularly, to an arc detection approach involving plasma generation.

BACKGROUND

[0003] Sputtering deposition, such as Physical Vapor Deposition (PVD),is a process for depositing thin, highly uniform layers of a variety ofmaterials onto many objects, for example depositing a metal layer over asubstrate such as a wafer used in forming integrated circuits (ICs). Ina direct current (DC) sputtering process, the material to be deposited(target) and the substrate to accept the deposited material (wafer) areplaced in a special vacuum chamber. The vacuum chamber is evacuated andsubsequently filled with an inert gas, such as argon, at low pressure.

[0004] The wafer is electrically connected to the anode of a highvoltage power supply, the anode being generally at or near earthpotential. The walls of the sputtering chamber are also placed at thispotential. A target, typically formed of metal, is placed in the vacuumchamber and electrically connected to the cathode of the high voltagepower supply. Alternately, the target is formed of an insulatingmaterial. An electric field is generated between the target (cathode)and an anode by the power supply. When a potential between the anode andcathode reaches 200-400 volts, a glow discharge is established in theinert gas in the superconducting region of the well known Paschen curve.

[0005] When a glow discharge operates in the superconducting region ofthe Paschen curve, valence electrons are torn from the gas and flowtoward the anode (ground), while the resulting positively-chargedionized gas atoms (i.e., plasma) are accelerated across the potential ofthe electric field and impact the cathode (target) with sufficientenergy to cause molecules of the target material to be physicallyseparated from the target, or “sputtered.” The ejected atoms travelvirtually unimpeded through the low pressure gas and plasma, some ofwhich land on the substrate and form a coating of target material on thesubstrate. The result, under ideal conditions, is a uniform cloud oftarget molecules in the chamber, leaving a resultant deposition ofuniform thickness on the chamber and its contents (e.g., the wafer).This coating is generally isotropic, conforming to the shape of theobjects in the chamber. A natural consequence of this action is that thetarget material wears or becomes thinner as more material is sputtered.

[0006] The processing of integrated circuits is reliant on theuniformity of coating resulting from the glow discharge process. Thevacuum chamber containing the discharge and target material is carefullydesigned to attempt to maintain a uniform electric field, and a glowdischarge is, in principle, sustainable over a range of electric fieldstrengths, again in accordance with the Paschen curve. However,uniformity of electric field cannot be maintained perfectly and theuniformity of the glow discharge and henceforth wear on the target isinfluenced by a number of factors, including thermal currents generatedin the chamber and other mechanical anomalies, such as targetmisalignment. To compensate for these anomalies, commercial PVDsputtering machines often incorporate a mechanism to rotate a largemagnet at constant speed above the target. This rotation serves todisturb the electromagnetic field in the chamber, focusing the region inwhich the plasma impinges upon the target on a smaller, moving area.Maintaining a constant power in the chamber while rotating the magnet ata constant rate improves the uniformity of wear of the target,increasing target life and generally maintaining a more uniformdistribution of molecular target material in the chamber. As the magnetrotates above the target, local geometric, thermal and other variationscause the lumped electrical impedance of the chamber to change. With thepower supply configured to deliver a constant power to the glowdischarge, the relation between chamber voltage and current required tomaintain constant power changes in accordance with the variation inimpedance. If one monitors the chamber voltage and current, a clearperiodic variation in the chamber voltage and current can be observed,with the period equal to that of the rotational period of the magnet.

[0007] Even with the rotating magnet mechanism in place to attempt tostabilize the glow discharge, certain conditions can result in a localconcentration of the electric field causing the glow discharge to passfrom the superconducting region of the Paschen curve into the arcingregion. Arcing during PVD results in an unintended low impedance pathfrom the anode to the target through electrons or ions in the plasma,the unintended path generally including ground, with the arcing beingcaused by factors such as contamination (i.e., inclusions) of the targetmaterial, inclusions within the structure (e.g., surface) of the target,improper target alignment (e.g., misalignment of cathode and anode),vacuum leaks, and/or contamination from other sources such as vacuumgrease. Target contaminants include SiO₂ or Al₂O₃.

[0008] Arcing during PVD is one cause of yield-reducing defects informing integrated circuits on semiconductor wafers. While normal metaldeposition is typically less than 1 micron thick, arcing causes alocally thicker deposition of metal on the wafer. When an arc occurs,the energy of the electromagnetic field of the chamber is focused on asmaller region of the target than intended (e.g., the neighborhood ofthe target defect), which can dislodge a solid piece of the target. Thedislodged solid piece of target material may be large relative to thethickness of the uniform coating expected on the wafer, and if a largepiece falls upon the wafer, it may cause a defect in the integratedcircuit being formed at that location. Subsequent photolithographyprocessing etches away various areas of the deposited metal layer,leaving metal conductor paths according to desired circuit patterns.Because arcing results in a localized defect (area) having a greaterthickness than the surrounding metal, the defect area may not bethoroughly etched in the subsequent processing, resulting in anunintended circuit path (i.e., short) on the chip. A semiconductor chiphas multiple metal layers separated by insulator layers, each of themetal levels formed by depositing, patterning and etching a metal layeras described above. A local defect in one layer can also distort anoverlying pattern imaged onto the wafer in a subsequent photolithographystep, and thus result in a defect in an overlying layer.

[0009] Manufacturing a wafer of modem integrated circuits can involvewell over a thousand individual processing steps, the value of the waferand consequently each individual integrated circuit die increasing witheach processing step. Arcing in a PVD sputtering apparatus used toprocess wafers into integrated circuits can render portions of the waferuseless for its intended purpose, thereby increasing manufacturingcosts. Using target materials free of arc-causing inclusions is one wayof minimizing integrated circuit fabrication defects; however, targetmaterial may become contaminated during its manufacture or thereafter.Discovering target contamination prior to sputtering operations so as toprevent arcing defects is costly, both in terms of time and expense. Notdiscovering arcing defects in a timely manner is similarly costly interms of random yield loss, for example by the manufacturer operating adeposition chamber until the target inclusion causing the arcing issputtered through. Furthermore, when a solid piece of the target isdislodged during an arc, the surface of the target may be furtherdamaged and the potential for future arcing in that neighborhoodincreases.

[0010] Absent real-time arc detection, corrective action is dependentupon the availability of parametric data. It is costly to measure thenumber of defective layers caused by arcing, for example via electricaltests designed to reveal shorts or by scanning the surface of waferswith a laser after metal deposition. These tests take time to run,during which production is delayed, or undetected yield loss occurs foran extended time. Since a defect such as a short at any level can impactintegrated circuit functionality, it is desirable to avoid damageresulting from arcing during sputtering deposition.

[0011] Accordingly, real-time arc detection permits fasteridentification of sources of yield loss, and detection of incipientfaults within the processing tool or target itself, both resulting inmore efficient integrated circuit fabrication applications.

[0012] As discussed above, arcs can throw solid material into thechamber, and it can be assumed that any such piece of solid materiallanding on a wafer of integrated circuits has a high probability ofdamaging at least one integrated circuit. One statistic indicative ofthe potential damage to a wafer of integrated circuits is therefore thenumber of arcs that occur during a process step. It is also reasonableto assume that the expected damage caused by an individual arc to anintegrated circuit wafer is a monotonically increasing function of theenergy delivered to the arc, since a violent arc is likely to spreadmore solid material over a wider area than a relatively “mild” arc. Asystem that can estimate both the number of arcs occurring during a PVDsputtering process step as well as the severity of the arcs in real timeis therefore a valuable tool in estimating the potential damage causedin a particular PVD sputtering step.

[0013] It is well known that when an arc occurs in a glow dischargeprocess, the magnitude of the lumped impedance of the chamber decreasesrapidly. When this occurs, the presence of series inductance in thedriving point impedance of the power delivery system, comprising powersupply and interconnection means, causes a rapid drop in the magnitudeof observed voltage between the anode and cathode of the chamber.Observing the chamber voltage and comparing it against a fixed thresholdis a common means of detecting the presence of an arc and one canreadily accomplish this by attaching a common oscilloscope to thecathode, with the ground of the oscilloscope probe attached to thechamber. Having an estimate of the average chamber processing voltage,which one can obtain visually by observing the voltage using a freerunning oscilloscope, one can set the trigger point of the oscilloscopeat a voltage greater than the expected voltage (the voltages observed insuch a manner are negative with respect to the oscilloscope reference).When the oscilloscope triggers, the resulting voltage waveform due tothe arc can be observed and one can also simultaneously observe thecurrent by means of an appropriate current probe. Systems have beendeveloped that emulate this method of detecting arcs and which count thenumber of occurrences so obtained over the course of a processing step.A known shortcoming of this approach is that the fixed trigger levelmust be set conservatively, as the chamber voltage varies periodicallywith magnet rotation as discussed above, as well as varying over thecourse of a PVD processing step due to thermal and other considerations.As such, such a system may miss arcs of small magnitude, whichnonetheless cause damage. A system that can more closely follow theactual, instantaneous expected chamber voltage would permit these arcsto be detected more readily, providing a more accurate estimate ofdamage.

[0014] In the PVD process used to produce integrated circuits, arcingconditions lasting less than 1 microsecond are commonly observed. Theseshort duration arcs are commonly called microarcs. Electronicallycontrolled analog or switching power supplies cannot react to this rapidchange in chamber impedance during a microarc. As a natural consequenceof the series inductance, the power supply delivers a near constantcurrent to the chamber during a microarc. Assuming that during an arcingcondition, all energy delivered by the power supply is focused on thearc, the energy delivered to an individual arc can be estimated by theintegral of the product of the power supply voltage times the (assumedconstant) current over the interval of the arc. Again, digitaloscilloscopes exist that permit the capture of both the chamber voltageand current waveforms during an arcing condition. Computer software,such as Tektronix “Wavestar” software, exists that can permit adigitally stored waveform to be uploaded to a computer, where thecaptured voltage and current waveforms can be subsequently multipliedpoint by point to compute instantaneous power and that power waveformintegrated over the duration of the arc to determine the overall energydelivered by an arc.

[0015] While useful for gaining an understanding of the arcingphenomenon in PVD applications, this method of computing arcs and arcenergy using an oscilloscope and a post processing computer is of littlevalue in production applications. Even modern handheld oscilloscopes arerelatively bulky instruments, and real estate in an integrated circuitclean room is extremely valuable. A stand alone post processing computeralso takes up valuable floor space and would likely need to be locatedoutside the clean room and connected to the oscilloscope by a network,adding latency in the transfer of data between the oscilloscope andcomputer. Furthermore, there is no means to tell a-priori the durationof an individual arc, or the frequency at which they might occur,leaving the problem of exactly how to set the controls of theoscilloscope. Oscilloscopes also have limited waveform storagecapability, and therefore prone to losing information at the times inwhich it is needed most, when there is much arcing activity during aprocess. A system so configured would render real time control anddecision making impractical.

[0016] Various aspects of the present invention address theabove-mentioned deficiencies and also provide for arc detection methodsand arrangements that are useful for other applications as well.

SUMMARY

[0017] The present invention is directed to an apparatus and method fordetecting arcs during plasma generation that addresses theabove-mentioned challenges and that provides a feedback method forcontrolling film deposition processes. The present invention isexemplified in a number of implementations and applications, some ofwhich are summarized below.

[0018] According to one example embodiment of the present invention, aplasma generation apparatus includes an arc detection arrangementcommunicatively coupled to a power supply circuit. The power supplycircuit has a cathode enclosed in a chamber, and is adapted to generatea power-related parameter. The arc detection arrangement is adapted toassess the severity of arcing in the chamber by comparing thepower-related parameter to at least one threshold.

[0019] According to other aspects of the present invention, the arcdetection arrangement is adapted to estimate arc intensity, arc durationand/or arc energy.

[0020] According to another example embodiment of the present invention,the arc detection arrangement is implemented using a programmable logiccontroller (PLC).

[0021] According to another example embodiment of the present invention,the PLC operates in concert with the arc detection arrangement tocompute an adaptive arc threshold value responsive to normal variationsin the impedance of the PVD chamber, said real time adaptive arcthreshold value communicated by the PLC to the arc detection apparatusin near real time.

[0022] According to another example embodiment of the present invention,the adaptive arc threshold value responsive to normal variations in theimpedance of the PVD chamber is computed by the arc detectionarrangement itself, with statistical data regarding both arcing activityand the adaptive arc threshold function communicated to the PLC in nearreal time.

[0023] The above summary of the present invention is not intended todescribe each illustrated embodiment or every implementation of thepresent invention. The figures and detailed description that follow moreparticularly exemplify these embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The invention may be more completely understood in considerationof the detailed description of various embodiments of the invention,which follows in connection with the accompanying drawings. Thesedrawings include:

[0025]FIG. 1 is a block diagram illustrating one example embodiment ofan arc detection arrangement, according to the present invention.

[0026]FIG. 2 is a block diagram illustrating one example implementationof a power supply interface module (PSIM) portion of an arc detectionarrangement, according to the present invention.

[0027]FIG. 3 is a circuit diagram illustrating one exampleimplementation of a PSIM voltage sensing circuit portion of an arcdetection arrangement, according to the present invention.

[0028]FIG. 4 is a circuit diagram illustrating one exampleimplementation of a PSIM current sensing circuit portion of an arcdetection arrangement, according to the present invention.

[0029]FIG. 5 is a circuit diagram illustrating one exampleimplementation of a PSIM power supply circuit portion of an arcdetection arrangement, according to the present invention.

[0030]FIG. 6 is a block diagram illustrating one example implementationof an arc detector unit (ADU) portion of an arc detection arrangement,according to the present invention.

[0031]FIG. 7 is a circuit diagram illustrating one exampleimplementation of an ADU voltage filter portion of an arc detectionarrangement, according to the present invention.

[0032]FIG. 8 is a circuit diagram illustrating one exampleimplementation of an ADU programmable threshold comparator portion of anarc detection arrangement, according to the present invention.

[0033]FIG. 9 is a block diagram illustrating one example implementationof an ADU arc detection logic unit (ADLU) portion of an arc detectionarrangement, according to the present invention.

[0034]FIG. 10 is a block diagram illustrating one example implementationof an ADLU counter unit portion of an arc detection arrangement,according to the present invention.

[0035]FIG. 11 is a timing diagram illustrating one exampleimplementation of clock logic unit (CLU) clock generation, according tothe present invention.

[0036]FIG. 12 is a logic diagram illustrating one example implementationof an ADLU digital signal processing interface logic arrangement portionof an arc detection arrangement, according to the present invention.

[0037] While the invention is amenable to various modifications andalternative forms, specifics thereof have been shown by way of examplein the drawings and will be described in detail. It should beunderstood, however, that the intention is not to limit the invention tothe particular embodiments described. On the contrary, the intention isto cover all modifications, equivalents, and alternatives falling withinthe spirit and scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION

[0038] The present invention is believed to be applicable to a varietyof different types of plasma generation applications, and has been foundto be particularly useful for film deposition applications, the latterbenefiting from a technique for responding to detected arcs during thegeneration of a plasma environment. Example embodiments described hereininvolve PVD sputtering techniques; however, the present invention can beimplemented in connection with a variety of systems, including thoseusing plasma-generating techniques such as plasma etching or PlasmaEnhanced Chemical Vapor Deposition system (PECVD).

[0039] While arcing events may never be wholly avoided, obtainingcertain detailed data regarding the severity of arcs occurring during asputtering process provides useful information from whichcompensatory-process decisions can be made. For instance, throughreal-time detection of a single arc of small magnitude, one mightsuspect the presence of minimal defects due to arcing on an affectedintegrated circuit die. Conversely, from real-time detection of a largequantity of arcs, or arcs of high severity, one might suspect thepresence of many defects, perhaps even reach a conclusion that an entireprocessing step is defective. Real time arc detection according to thepresent invention permits manufacturing decisions to occur in real time,or nearly so. For example, where a processing step is suspected as beingdefective due to detection of significant quantity or severity ofarcing, the PVD process step may be terminated before further damage canoccur. At the end of a PVD processing step, whether completed normallyor terminated per above a decision to repair or discard the wafer can bemade before further processing steps are initiated. If an initialprocessing step is deemed defective through real-time detection ofsignificant arcing, and processing costs to the present stage ofmanufacturing the wafer are low, it may be cost-effective to discard thewafer. If arcing occurs during a latter processing step, for which thecost of processing a wafer to the affected step is high, it may becost-effective to chemically etch or physically polish the wafer toremove the defective deposition layer and reprocess the wafer.Additionally, detection of arcing activity on a wafer to wafer basis ofan individual PVD system in which no or minimal previous arcing activityis observed may be indicative of the development of an incipientequipment fault condition that can be corrected by schedulingappropriate equipment maintenance during scheduled equipment inactivity.The key is timely recognition of the increased probability of defectsdue to arcing.

[0040] For a particular PVD system, the power supply to drive theprocess attempts to regulate power delivered to the chamber. Theimpedance of the chamber elements, including the anode, cathode andchamber environment between the anode and cathode, is in series with theimpedance of the plasma-generating power supply circuit. The relationbetween voltage and current to maintain a constant power in a plasma isdependent upon the impedance of the chamber elements, including theconductivity of the particular target material itself which is subjectto change as a result of the sputtering process.

[0041] When an arc develops in the sputtering chamber, the magnitude ofthe impedance of the chamber drops rapidly, thereby changing theimpedance of the plasma-generating power supply circuit. The powersupply and distribution circuit contains significant series inductance,limiting the rate at which current can change in the circuit. A rapiddrop in chamber impedance therefore causes a rapid decrease in themagnitude of chamber voltage due to this inductive component. Thiscollapse in chamber voltage magnitude is often sufficient to extinguishthe arcing condition and re-establish a glow discharge before seriousdamage to the chamber, the power supply, or the target can result.Typically, arcing events occur (and disappear) more quickly than theelectronics regulating the power supply are able to react, so even ifcorrective action is initiated by the electronics, some damage to thewafer is possible. As discussed previously, the probability that an itembeing coated will suffer some form of defect, such as a non-uniformcoating on a wafer, increases as a result of each arcing event. Becausethe chamber voltage drops rapidly when an arcing event occurs, anunexpected voltage drop below a pre-defined or adaptive voltagethreshold level can be used to define the occurrence of an arcingcondition.

[0042] The voltage threshold delineating the existence of an arcingevent is dependent upon the nominally applied (i.e., non-arcing),perhaps time varying chamber voltage according to one exampleimplementation. The non-arcing chamber voltage applied to produce a glowdischarge is dependent on many factors including the condition andcomposition of the target (which affects circuit impedance). All othercircuit impedances remaining constant, a higher chamber voltage isrequired to produce a glow discharge using a relatively less-conductivetarget material, conversely a lower chamber voltage is required toproduce a glow discharge using a relatively-higher conductive targetmaterial. For example in one sputtering chamber implementation, thechamber voltage required to uniformly deposit aluminum is nearly twicethe chamber voltage required to deposit copper. The chamber voltagerequired to uniformly deposit aluminum can also vary from chamber tochamber, being dependent on the balance of circuit impedance includingthe power supply and other chamber elements. Furthermore, as the targetages and more material is sputtered, the power required to maintain auniform deposition rate must be modified (e.g., increased). As therequired applied voltage changes, it follows that the associatedthreshold voltage at which an arcing condition is determined should alsobe changed.

[0043] According to a general example embodiment of the presentinvention, a plasma generation apparatus includes an arc detectionarrangement communicatively coupled to a power supply circuit. The powersupply circuit has a cathode enclosed in a chamber, and the power supplycircuit is adapted to generate a power-related parameter (e.g., avoltage signal). The arc detection arrangement is adapted to assess theseverity of arcing in the chamber by comparing the power-relatedparameters to at least one threshold. Parameters determining arcingseverity are process-dependent and include, but are not limited to, arcquantity, arc rate, arc intensity, arc duration, and/or arc energy.

[0044] According to one implementation, the arc detection arrangementfor a sputtering process monitors a sputtering chamber voltage anddetects an arcing condition whenever the chamber voltage magnitude dropsbelow a preset arc voltage threshold value.

[0045] According to one aspect, the power-related parameter (e.g.,voltage) threshold value is variable over a range of power-relatedparameter values. Any threshold may be programmable, and may becontrolled by a logic arrangement, for example being electronicallycontrolled by a remote logic arrangement. In one example implementation,the voltage threshold value demarking an arc occurrence is computed inresponse to an estimate of nominal chamber voltage magnitude, thenominal chamber voltage magnitude being the chamber voltage necessary toproduce a glow discharge (i.e., generate a plasma) during non-arcingconditions. In one example implementation, any threshold may behysteretic, or programmed to be hysteretic having a “reset” valuedifferent from a “surpass” value.

[0046] According to one aspect of the present invention, the arcdetection arrangement is further adapted to count arcing conditions(events) responsive to the at least one threshold. A rate of detectedarcing condition occurrences may be determined therefrom.

[0047] According to another aspect, the arc detection arrangement isfurther adapted to measure arcing duration responsive to comparing thepower-related parameter to the at least one threshold. For example, thearc detection arrangement includes a clock and a digital countingarrangement in one implementation. The clock provides a clock signalhaving a fixed period, and the digital counting arrangement is adaptedto count the clock signal periods responsive to comparing thepower-related parameter to at least one threshold. According to afurther aspect of the present invention, the duration of arcingconditions is assessed by comparing the power-related parameter to atleast one threshold. According to one example implementation, theduration of arcing conditions is accumulated over a fixed period.According to another example implementation, the duration of arcingconditions is accumulated until the duration threshold is reached, oruntil the accumulated duration is reset.

[0048] According to another aspect, the arc detection arrangement isfurther adapted to measure arcing intensity responsive to comparing thepower-related parameter to the at least one threshold. In one exampleimplementation, the arc detection arrangement is adapted to compare thepower-related parameter to a plurality of thresholds arranged atdifferent values thereby ascertaining the extent or range of change(from nominal) to the power-related parameter during an arcing event. Inone example embodiment, the threshold corresponding to the largestobserved voltage magnitude drop provides a lower bound to the energyestimate, while the next larger voltage drop threshold (which the systemis observed to not exceed) provides an upper bound to the energyestimate.

[0049] According to another example embodiment of the present invention,the arc detection arrangement is adapted to measure arcing duration andintensity responsive to comparing the power-related parameter to the atleast one threshold. In one implementation, the arc detectionarrangement is further adapted to measure arcing energy responsive tocomparing the power-related parameter to the at least one threshold,arcing energy being proportional to the product of the arcing durationand the arcing intensity, and assessment of arcing severity being afunction of the arcing energy (i.e., the product of arcing intensity andarcing duration). According to one particular implementation, aplurality of thresholds are used to determine a plurality of durations,in order to estimate (i.e., approximate, or integrate) an area boundedby a power-related parameter (e.g., chamber voltage) versus time plotduring a depression in the voltage due to arcing. An arcing energyproportional to the bounded area for each arcing event is used to assessthe severity of arcing. According to a further implementation, the arcdetection arrangement is further adapted to accumulate arcing energyover a plurality of arcing events, for example by summing the productsof arcing intensity and arcing duration to assess the severity ofarcing.

[0050] According to another example implementation, the arc detectionarrangement includes a power-related parameter band-limiting filter as ameans to prevent aliasing prior to digitizing the power-relatedparameter. Commonly understood digital signal processing techniques areapplied to this digitized power-related parameter to reduce oraccentuate certain frequency response characteristics of thepower-related parameter. This digitally signal processed parameter maythen be compared directly against a similarly digitized version of theat least one threshold.

[0051] According to another example implementation, a digitally signalprocessed parameter per above is used to compute at least one timevarying threshold value, responsive to certain observed characteristicsof one or more power-related parameter over the course of the PVDprocess.

[0052] According to another example embodiment of the present invention,a plurality of power-related parameters are compared to a plurality ofthresholds in assessing the severity of arcing as described above. Forexample, in addition to chamber voltage, power supply current ismonitored and used in detecting arcing events, an arcing event beingdetermined whenever the current magnitude exceeds a preset currentthreshold value.

[0053] According to another example embodiment of the present invention,a logic arrangement is communicatively coupled to the arc detectionarrangement, and adapted to process the arcing data collected by the arcdetection arrangement. In one implementation, the logic arrangement isadapted to interface with the arc detection arrangement, the logicarrangement having a data network and additional external devices suchas process controllers, monitors and logic arrangements. In oneparticular application, the logic arrangement is a programmable logiccontroller (PLC).

[0054] According to another example embodiment of the present invention,arc severity in a plasma generation chamber is assessed by timing an arcduration, which is derived by comparing a power-related parameter to atleast one arc intensity threshold, and adding the arc duration to anaccumulated arcing duration. Further example implementations of themethod include measuring the power-related parameter during non-arcingplasma generation and automatically adjusting the arc intensitythreshold(s) responsive to measuring the power-related parameter;counting arc occurrences; and/or assessing arc severity as a function ofarc intensity, arc duration and/or the product thereof.

[0055] According to another embodiment of the present invention, arcingseverity in a plasma generation chamber is assessed by determining anarc intensity, which is derived by: comparing a power-related parameterto at least one arc intensity threshold, timing an arc durationresponsive to comparing a power-related parameter to at least one arcintensity threshold, computing arc energy as a function of arc intensityand arc duration, and then adding the arc energy to an accumulatedarcing energy. Further example implementations of the method includemeasuring the power-related parameter during non-arcing plasmageneration and automatically adjusting the at least one arc intensitythreshold responsive to measuring the power-related parameter; countingarc occurrences responsive to comparing the power-related parameter tothe at least one arc intensity threshold; and/or employing a hystereticarc intensity threshold; and/or transmitting information representativeof arcing to a logic arrangement on command via a shared data path, theinformation being one selected from a group that includes quantity ofarc occurrences and accumulated arcing duration. The power-relatedparameter is a function of plasma generation chamber voltage in oneparticular implementation; the power-related parameter being formed as adigital representation of plasma generation chamber's operatingcharacteristics in another implementation.

[0056] In describing the following particular example embodiment of thepresent invention, reference will be made herein to FIGS. 1-12 of thedrawings in which like numerals refer to like features of the invention.

[0057]FIG. 1 illustrates an example embodiment of an arc detectionarrangement 100 of the present invention. Arc detection arrangement 100is used, for example, in a pressure vapor deposition (PVD) process stepin integrated circuit manufacture and other processes where uniformmaterial deposition is desired. A PVD sputtering system includes adeposition (vacuum) chamber 10 containing a gas 15, such as argon, atlow pressure. A target 20 formed of metal is placed in vacuum chamber 10and electrically coupled as a cathode to a power supply 30 via anindependent power supply interface module (PSIM) 40. According to oneexample implementation, power supply 30 and chamber 10 are coupled usinga coaxial interconnecting cable 35. A substrate (wafer) 25 is coupled asan anode to power supply 30 through a ground connection. The vacuumchamber is also typically coupled to ground potential. According toanother example implementation, the anode is coupled to power supply 30directly. Rotating magnet 27 is included to steer the plasma to maintainuniform target wear. PSIM 40 includes a buffered voltage attenuator 44adapted to sense the chamber voltage and provide an analog signal to anArc Detection Unit (ADU) 50 via voltage signal path 42 responsive to thechamber voltage. The PSIM also includes a Hall effect-based currentsensor 46 adapted to sense the current flowing to the chamber andprovide an analog signal via current signal path 48 to the ADUresponsive to the chamber current. In another example implementation,the target is formed of an insulating material. ADU 50 iscommunicatively coupled to a logic arrangement 60, for example aprogrammable logic controller (PLC) or communication tophat via a localdata interface 70. Logic arrangement 60 may be coupled to a data network80, for example a high level process control network such as an EGModbus-Plus TCP-IP on Ethernet.

[0058] An electric field is generated between the target (cathode) andanode by the power supply causing the gas in the vacuum chamber toionize. Ionized gas atoms (i.e., plasma) are accelerated across thepotential of the electric field and impact the target at high speed,causing molecules of the target material to be physically separated fromthe target, or “sputtered.” The ejected molecules travel virtuallyunimpeded through the low pressure gas and plasma striking the substrateand forming a coating of target material on the substrate. Typicaltarget voltage for sputtering aluminum is a steady state magnitude ofapproximately 450 volts dc (VDC).

[0059]FIG. 2 illustrates one example embodiment of PSIM 40. PSIM 40derives signals representative to the chamber voltage and current.Coaxial cable 35 electrically couples the power supply to the chamber.Cable 35 has an outer conductor 210 nominally at ground (earth)potential, and a center conductor 215 biased negatively with respect tothe outer conductor. Current in cable 35 is measured using a Hall effecttransducer 220 or other current transducing device. Transducer 220 isarranged to selectively measure current flowing in center conductor 215,indicative of the total current flowing to the chamber. Center conductor215 of cable 35 passes through an aperture 225 in Hall effect transducer220. To expose center conductor 215, outer conductor 210 is interruptednear transducer 220, and outer conductor current is directed aroundaperture 225 via current shunt 230 coupled to outer conductor 210. Thearrangement of Hall effect transducer 220 simplifies packaging of thePSIM while simultaneously providing a high level of galvanic isolationbetween cable 35 and the output signals of transducer 220. The presentinvention is not limited to using a Hall effect transducer. Other meansfor deriving a signal responsive to the current flowing from chamber 10to power supply 30 are contemplated, including but not limited to anarrangement including a current shunt with appropriate voltageisolation, and means based on certain piezo-resistive currenttransducers.

[0060] Transducer 220 has a first output terminal 222 carrying currentsignal I− and a second output terminal 224 carrying current signal I+.First and second transducer output terminals are electrically coupled toan Isense circuit arrangement 240, first transducer output terminal 222being coupled to Isense circuit first input terminal 242, and secondtransducer output terminal 224 being coupled to Isense circuit secondinput terminal 244. Isense circuit arrangement 240 also has a firstoutput terminal 246 carrying signal IPSIM−, and a second output terminal248 carrying signal IPSIM+. Isense circuit receives current signals I+and I−, and generates a differential voltage between signals IPSIM+ andIPSIM− responsive to the current-flowing from the chamber to the powersupply.

[0061] Vsense circuit 250 measures the potential difference betweencenter conductor 215 and outer conductor 210, and generates adifferential responsive to the potential difference. The Vsense circuitincludes a first input terminal 252 coupled to inner conductor 215 andcarrying voltage signal V−. The Vsense circuit also includes a secondinput terminal 254 coupled to outer conductor 210 and carrying voltagesignal V+. The Vsense circuit has a first output terminal 256 carryingoutput voltage signal VPSIM−, and a second output terminal 258 carryingoutput voltage signal VPSIM+.

[0062] Coaxial cable 35, connecting power supply 30 to vacuum chamber10, is terminated in standard commercial UHF type connectors in oneexample implementation. According to one aspect of the presentinvention, the mechanical packaging of PSIM 40 is arranged andconfigured such that cable 35 can be de-terminated at one end, insertedthrough aperture 225 of PSIM 40 and re-terminated to complete a circuitbetween power supply 30 and chamber 10. In an alternate implementation,PSIM 40 includes UHF type connectors so that PSIM 40 can be inserted inthe circuit of cable 35 between power supply 30 and chamber 10.

[0063]FIG. 3 illustrates one example implementation of Vsense circuit250 to provide differential output voltage signals responsive to theinstantaneous voltage difference between the cathode and anode of thePVD system. The example Vsense circuit illustrated in FIG. 3 providesfor a very high impedance between the voltage signals present at itsinput terminals and the voltage signals provided at its outputterminals. The positive input voltage signal 254 (V+) is derived fromthe outer conductor 210, and the negative voltage signal 252 (V−) isderived from inner conductor 215 of power supply cable 35.

[0064] According to the example implementation illustrated, resistornetworks R3 and R4 provide an attenuation factor of 500:1 to eachrespective input voltage signal with respect to a reference plane,GNDANALOG. Each of the resistor networks R3 and R4 have a nominalresistance of approximately 20 Megaohms between the network senseterminal (pin 1) and the reference plane (pin 3). Resistive networks R3and R4 can be implemented using, for example, thick film high voltagedivider networks such as Ohmcraft P/N CN-470. An applied voltage of 1000volts between 252 (V+) and 254 (V−) causes a current of 25 microamperesto flow into pin 1 of R4 and out of pin 1 of R3. Pin 3 of each of thesevoltage attenuators (i.e., resistive network) is coupled to thereference plane, GNDANALOG. Since each of the voltage attenuatorsprovide a 500:1 attenuation, a differential voltage measured betweenpins 2 of each resistive network (i.e., between attenuated signal VPSA+at pin 2 of R4 and attenuated signal VPSA− at pin 2 of R3) areattenuated by 500:1, and this measurement is independent of the voltagedifference between either V+ and GNDANALOG, or V− and GNDANALOG.

[0065] The PVD sputtering chamber 10 has radio frequency (RF) energyapplied in one example implementation, to stabilize the plasma.Capacitors C2, C3 and C5 of Vsense circuit 250 significantly attenuates(i.e., filters) this high frequency “noise”. According to one exampleimplementation, the combination of C2 and R3 has an effective pole atabout 22 kHz.

[0066] As discussed above, the differential voltage appearing betweenVPSA− and VPSA+ is a band limited representation of the signal appearingbetween V− and V+, with a nominal DC attenuation factor of 500:1. Theequivalent DC Thevenin source impedance between VPSA− and VPSA+ is high(on the order of 80 kOhms) and therefore not suitable for transmissionover large distances or into low impedance loads. Therefore, adifferential instrumentation operational amplifier U2; for example anLT1920 instrumentation operational amplifier, is incorporated in theVsense circuit to serve as a low impedance voltage follower. OperationalAmplifier U2 provides high impedance inputs (pins 2 and 3), which willnot significantly load the outputs of attenuators R3 and R4. Pin 2 ofresistive network R3 is coupled to the inverting input (pin 2) of U2 andPin 2 of resistive network R4 is coupled to the non-inverting input (pin3) of U2. Resistor RG2 sets the voltage gain of U2 and is selected toyield a gain of 1V/V in the example embodiment. The resulting output ofU2 (pin6) is a single ended low impedance voltage source relative toGNDANALOG that closely follows the voltage developed between VPSA− andVPSA+.

[0067] The output of U2 (pin 6) is coupled to the center terminal of aBNC type connector, J2, and carries the signal VPSIM+ 258. The outerconnector of BNC type connector J2 carries signal VPSIM− 256 and iscoupled to the reference plane GNDANALOG. The resulting differentialvoltage between signals VPSIM+ and VPSIM− is band limited with respectto the differential input signals V+ and V−, and has a nominal DCresponse of 2 mV/V.

[0068] In one embodiment, the Hall effect type DC current transducer 220when coupled to an appropriate load impedance placed between signals 244(I+) and 242 (I−) generates a current responsive to current flowing ininner power supply conductor 215. In one particular embodiment, using amodel LA25-P Hall effect type DC current transducer manufactured by LEM,the current signal developed by DC current transducer 220 isapproximately proportional to the total current passing through aperture220 at a ratio of 1000:1. Thus a 1 ampere signal passing throughaperture 220 generates a constant current of 1 mA flowing through animpedance placed between 244 (I+) and 242 (I−), within the limits of theDC current transducer design. FIG. 4 illustrates one exampleimplementation of a current sensing arrangement, Isense circuit 240 thatgenerates a voltage responsive to the current developed by the exampleLA25-P Hall effect type DC current transducer. In this example, signalI− is coupled to the reference plane GNDANALOG of PSIM 40. An impedancecomprising 100 Ohm resistor R6 in parallel with a low pass filtercomprising resistor R7 and capacitor C10 is coupled between I+ and I−.Ignoring the relative high impedance of the low pass filter, the currentI+ flows through resistor R6 and returns to current transducer 220through I−. The net result of the circuit comprising current transducer220 and resistor R6 is a voltage across R6 proportional to the currentflowing through aperture 222, with the constant of proportionality 100mV/Ampere. The low pass filter comprising resistor R7 and C10 has anominal 3 dB cutoff frequency of 23 kHz, which serves to remove anystray noise from the current signal, including the aforementioned RFcomponent sometimes included to stabilize the glow discharge. The lowpass filter output, V_(IL) in FIG. 4, is a band limited representationof the voltage developed across R6 by current transducer 220. Aninstrument amplifier U3, such as an LT1920, serves as a low impedancevoltage follower responsive to the signal V_(IL) by coupling V_(IL) tothe non-inverting input (pin 3) of U3, with inverting input of U3 (pin2) coupled to GNDANALOG through resistor R5. Resistor RG1 serves to setthe gain of instrumentation amplifier U3 to 1V/V in the present example.The output terminal (pin 6) of U3 carries signal IPSIM+ and is coupledto the center conductor of a BNC type connector, J3. The outer conductorof BNC type connector J3 is coupled to GNDANALOG and designated signalIPSIM−. The voltage developed between IPSIM+ and IPSIM− is consequentlya signal responsive to the current flowing in aperture 220, band limitedto a cutoff frequency of approximately 23 kHz and with a constant ofproportionality of approximately 100 mV/Ampere.

[0069]FIG. 5 illustrates one example implementation of a PSIM powersupply circuit 500 (not shown in FIG. 2) and required to biasinstrumentation operational amplifiers U2 and U3. A dual power supplymodule U1, for example Astrodyne model FDC10-24D15, generates thenominal +15 VDC and −15 VDC used to bias PSIM amplifiers U2, U3, andcurrent sensor CS1. Module U1 derives its bias power from an externalnominal 24 VDC power source through connector J1, pins 1 and 3, pin 1being biased more positively than pin 3. Pin 3 of connector J1 iscoupled to the −Vin terminal of power supply module U1. Pin 3 ofconnector J1 is coupled to the +Vin terminal of power supply module U1through a Schottky Barrier Diode D2 to protect module U1 from damageshould the polarity of power supplied to connector J1 be accidentallyreversed.

[0070] Power supply module U1 has three output terminals, +Vo, −Vo andCom. A +15 VDC signal is provided at terminal +Vo and a −15 VDC signalis provided at terminal −Vo. Terminal Com is coupled to the referenceplane GNDANALOG. Pin 2 of connector J1 is also coupled to GNDANALOG as acommon potential in the application as required. Resistors R1 and R2 andlight-emitting diode D1 are coupled in series between the +15 VDC biasvoltage and the −15 VDC bias voltage to provide an indication that PSIMpower supply circuit 500 is operational.

[0071] Arcing is defined as a collapse in the chamber voltage magnitudethat crosses a threshold voltage. Upon occurrence of an arc, the chamber(target) voltage magnitude rapidly decreases (i.e., is closer to groundpotential), and chamber current increases more slowly due to seriesinductance, from steady state (i.e., non-arcing) conditions. Theprogrammed threshold voltage is a predetermined chamber voltage at orbelow which an arcing state is determined and may be a constant value ora time varying function of the nominal, expected, possibly time varyingchamber voltage. A non-arcing state is determined to occur when thechamber voltage is above the threshold voltage. According to analternate example implementation, the threshold voltage is determinedfrom a period including a non-arcing state, and an arcing state isdefined to occur whenever the chamber voltage is below the voltagethreshold. Multiple threshold voltages can be used to determine themagnitude of an arc (i.e., voltage dip or “severity”). For example, anarc that crosses a −200V threshold but not a −100V threshold may beconsidered less severe than an arc that crosses both thresholds.

[0072] The ADU 50 includes a digital signal processor to processes thesignals received from the PSIM to provide digitally-filteredrepresentations (e.g., digital signals), of the chamber voltage andcurrent signals respectively, to a logic arrangement. According to oneexample implementation, the ADU includes an analog-to-digital converter(A/D)

[0073] The ADU is further adapted to set at least one programmable arcthreshold voltage. In a further implementation, the ADU is also adaptedto set at least one hysteresis threshold voltage. According to oneaspect, the respective thresholds can be set at any point along acontinuous spectrum; this can be affected via a potentiometer settingcontrolling a comparator circuit arrangement. According to anotherexample implementation, the respective thresholds are set digitally viaa digital to analog converter, or via a plurality of discrete thresholdlevels achieved by switching specific circuit components into acomparator circuit arrangement, for example by selecting theconfiguration of a resistive network. To identify the hysteresisthreshold(s), the ADU provides a programmable hysteresis function todetect arcs that manifest themselves slowly. Both the arc (voltage)threshold and hysteresis function can be set or programmed directly inthe ADU, or the threshold values may be optionally controlled by aremote device communicatively coupled to the ADU, for example through astandard Momentum communication tophat via a Ethernet, Modbus Plus,Devicenet, or other data network. In one example implementation, the ADUis tightly coupled to a programmable logic controller (PLC) such as aMomentum M1-E via a high speed proprietary serial interface, and the PLCcan be programmed to continuously adapt the arc voltage threshold andhysteresis function in real time according to a real time adaptivealgorithm.

[0074]FIG. 6 illustrates one example embodiment of an Arc Detector Unit(ADU) based on a Digital Signal Processor and Controller (DSPC) 630,which includes a digital signal processor (DSP) integrated circuit, suchas model TMS320F2407 available from Texas Instruments, Inc., of Dallas,Tex., and additional commercially available integrated circuit devicesused to develop signals to control and communicate with externaldevices. An example of such a device is an address decoder commonly usedto divide the address space of a DSP into ranges and select one of aplurality of external integrated circuit devices for data transfer toand from the DSP. Development of these signals using integrated circuitsis in accordance with the timing requirements of the digital signalprocessor when accessing external devices and is well understood bythose skilled in the art of designing and implementing microprocessorand microcontroller based systems.

[0075] The DSP illustrated includes 16 analog input channels that can besampled and digitized by an integral 10-bit analog to digital converter635. Signals presented to these analog input channels, such as thesignals I_(CH) 616 and V_(CH) 614, to be discussed subsequently, can besampled and digitized by the DSP at a user programmable rate. In oneexample implementation, this rate is programmable up to 10 kHz perchannel. In another example implementation, a software program executedwithin the DSP provides for the selection and application of one of aplurality of digital finite impulse response filters to the sampled datasignals. DSPC 630 also provides control signals to a ProgrammableThreshold Comparator function 620 to set the threshold and hysteresisvalues of the Programmable Threshold Comparator. In addition, DSPC 630provides control and data paths to and from a high speed Arc DetectorLogic Unit (ADLU) 640, which works in conjunction with ProgrammableThreshold Comparator 620 to accumulate arc statistics such as number ofarcs and total arc time. DSPC 630 communicates with an external logicarrangement 60, such as a networked communication tophat or ProgrammableLogic Controller (PLC), via local data interface 70, for example aproprietary ATII interface. Examples of information that can befurnished from the ADU to the external logic arrangement 60 are thefiltered chamber voltage and current, the number of individual arcingevents and other values indicative of arc severity, as determined by ArcDetector Logic Unit 640. Examples of data that can be accepted by theADU from the external logic arrangement are the instantaneous arcthreshold voltage and hysteresis, and logical control signals thatcontrol the Arc Detector Logic Unit.

[0076] The fundamental sensed process inputs of Arc Detector Unit 50 arethe differential output signals from the Vsense circuit (VPSIM+ andVPSIM−) and the Isense circuit (IPSIM+ and IPSIM−) of PSIM 40. Referringagain to FIG. 6, these signals drive analog signal conditioner 610.Analog signal conditioner 610 converts the respective differentialanalog signals to single ended signals usable by the rest of the ADU.Signal conditioner 610 also provides band limiting filters for therespective input analog signals so that DSPC 630 can apply digitalsignal sampling and processing algorithms without the phenomenoncommonly called “aliasing”. Analog signal conditioner 610 includes threeoutput terminals, output terminal 612 providing signal V_(CH)′, outputterminal 614 providing signal V_(CH), and output terminal 616 providingsignal I_(CH). Signal V_(CH)′ is a single-ended version of the signalemanating from the PSIM and derived from the signals V_(PSIM)+ andV_(PSIM)−, and feeds a Programmable Threshold Comparator 620. The signalV_(CH) is a band-limited, single-ended version of the differentialsignals VPSIM+ and VPSIM−, developed by Vsense circuit 250 of PSIM 40.The signal I_(CH) is a band-limited, single-ended version of thedifferential signals IPSIM+ and IPSIM− developed by Isense circuit 240PSIM 40. Signals I_(CH) and V_(CH) are input to analog to digitalconverter 635 of DSPC 630. Processing performed on these analog signalsby Digital Signal Processor and Controller 630 will be discussed in moredetail subsequently.

[0077]FIG. 7 illustrates one example implementation of a voltage filterportion 700 of signal conditioner 610 using commercially available quadoperational amplifier integrated circuits, such as Analog Devices modelAD824 for U27:A-D. Amplifier U27A and resistors R108, R107, R115 andR116 form a differential amplifier that converts the differentialvoltage between V_(PSIM1)+ and V_(PSIM1)−, to a single ended voltagerelative to the reference plane GNDANALOG at the output (pin 1) ofamplifier U27A. The output of amplifier U27A is signal 612 in FIG. 6,and labeled V_(CH)′. V_(CH)′ couples to the internal network comprisingamplifiers U27B, U27C and U27D and the remaining passive resistors,which form a six-pole Butterworth filter with a 3 dB crossover atapproximately 2500 Hz. The output of this filter, labeled 614 (V_(CH))in FIG. 6, is the signal provided to the analog to digital converter 635of DSPC 630. Assuming a 10 kHz sample rate of analog to digitalconverter 635, the 6 pole Butterworth filter, shown in FIG. 7,attenuates signals above the Nyquist rate of 5 kHz at better than −80dB, thus minimizing the effects of aliased signals on the sampledvoltage signals.

[0078] The current filter portion of signal conditioner 610 thatgenerates signal I_(CH) from PSIM signals IPSIM+ and IPSIM− is identicalin topology to that of the voltage filter, but the current signalequivalent to V_(CH)′ is not used in the example embodiment. The outputof the current filter, I_(CH) is similarly band limited by an identicalButterworth filter with 3 dB crossover at approximately 2500 Hz.

[0079] Referring again to FIG. 6, functionally Programmable ThresholdComparator 620 compares signal V_(CH)′, responsive to the magnitude ofthe difference between the chamber voltage signals from the PSIM,against a programmable voltage value set and controlled by DSPC 630. Theoutput 622 of Programmable Threshold Comparator 620 is the signal \ARC.Programmable Threshold Comparator 622 asserts \ARC a logic “1” valuewhenever the sensed differential chamber voltage magnitude exceeds theprogrammed threshold value and a logic “0” value whenever the senseddifferential chamber voltage magnitude is less than the programmedthreshold value. A programmable hysteresis is applied to the programmedthreshold value in a manner to be described subsequently, to minimizethe effects of a noisy V_(CH)′ signal applied to Programmable ThresholdComparator 620. Hereinafter, the condition in which the signal \ARC(i.e., “not ARC”) is in the logic “0” state (chamber voltage below apredefined threshold) is referred to as the ARCING condition and thecondition in which the \ARC signal is in the “1” state (chamber voltageabove a predefined threshold) is referred to as the NON_ARCINGcondition.

[0080]FIG. 8 illustrates one example implementation of a ProgrammableThreshold Comparator 620. Programmable Threshold Comparator 620 includesa commercially available analog comparator integrated circuit U12:A,such as an LM319M. GNDANALOG is the analog reference plane; DGND is adigital reference plane used by the logic signals of DSPC 630 and otherdevices and integrated circuit bias voltage is at +5 V. Functionally,analog comparator U12:A has an output terminal (pin 12), an invertinginput terminal 1IN− (pin 5), and a non-inverting input terminal 1IN+(pin 4). The output terminal (pin 12) of U12:A generates signal 622 inFIG. 6 and labeled \ARC. Nominally, the logic signal present at theoutput terminal is denoted as logic “1” whenever the signal at thenon-inverting input is at a higher voltage than the signal at theinverting input terminal. Conversely, the logic signal present at theoutput terminal is a logic “0” whenever the signal at the non-invertinginput is at a lower voltage than the signal at the inverting inputterminal. The signal present at the output terminal whenever the tworespective signals at the input terminals are identical is undefined. Inan embodiment of the present application, device U12:A is arranged tohave an open collector output. Resistor R27 is a pull-up resistor,coupled to a +3.3 V bias supply used to power the DSP, ADLU and othercircuitry. Resistor R25 is nominally 200 kohms and provides a minimumlevel of hysteresis to analog comparator U12:A to effect smooth logicstate transitions without oscillation when U12:A encounters slowlyvarying input signals. Resistors R28, R29 and R26 along with a precision3.00 volt reference voltage source connected to R26 provide an affinetransformation of the scaled, instantaneous chamber voltage signalV_(CH)′, of the form:

V _(CS)=0.6V _(CH)+1.0  (Eqn. 1)

[0081] where V_(CS) is that signal appearing on the non-inverting input,pin 4 of analog comparator U12:A in FIG. 8. Thus, according to Eqn. 1, a0 V signal at V_(CH)′ appears as a 1 V signal at pin 4 of analogcomparator U12:A, and a 2.5 V signal at V_(CH)′ appears as a 2.5 Vsignal at pin 4 of analog comparator U12:A. This affine transformationis applied to maintain the inputs of analog comparator U12:A within arange required by the analog comparator manufacturer to guarantee linearoperation over a range of chamber operating voltages between 0 and −1250volts. In one particular embodiment, the 3.00 volt reference for theinternal analog to digital converter is provided by a commerciallyavailable bandgap regulator, Model REF193, manufactured by NationalSemiconductor.

[0082] Programmable threshold voltage signal, V_(TH), is provided to theinverting input of analog comparator U12:A (pin 5) to set the chambervoltage at which the ADU transitions between the NON_ARCING and ARCINGstates. A programmable hysteresis value, generated in a manner to bedescribed subsequently, permits the value of V_(TH) to be modal. A userspecified value can be programmed to set the chamber voltage magnitude,V_(THNA), at which the system transitions from the NON_ARCING to theARCING state and a second voltage magnitude value, V_(THAN), to set thevoltage at which the system transitions from the ARCING to theNON_ARCING state. Device U13 is a dual 14-bit digital to analogconverter (DAC), for example model AD5322 manufactured by AnalogDevices, Inc., which is used to set the two values of V_(TH). It has twooutput terminals labeled, Vo _(—) _(A) and V_(o) _(—) _(B), the voltagevalues of which are set by the DSP using a standard serial peripheralinterface (SPI) feature, integral to the DSP. The signals labeledSPISIMO, SPICLK, \DAC 1_SELECT and \LDAC are signals used by DSPC 630 toprogram a digital value ranging between 0 and 4095 for each of the twoDAC channels. The precision 3.00 Volt reference described above isapplied to U13, with the result that each DAC output generates anindependent, analog output in the range 0-3.00 volt, in proportion tothe ratio of the programmed digital value to the maximum value 4095.Output terminal V_(o) _(—) _(B) (pin 6), generated from the value of DACB of U13 is coupled to the non-inverting input of operational amplifierU14:A, and is labeled V_(OB). As will be shown subsequently, the signalV_(OB) determines the voltage threshold at which comparator U12:Atransitions from the NON_ARCING to the ARCING state, V_(THNA). Thesignal V_(OA), generated by the output of DAC A of U13 (pin 5) iscoupled to the input terminal of analog switch U15:D, and as will alsobe shown subsequently, is used along with signal V_(OB) to set thevoltage threshold, V_(THAN) at which comparator U12:A transitions fromthe ARCING to NON_ARCING state. According to one example implementation,U15:D is part of a quad analog switch, for example DG201HS manufacturedby Intersil and others. The output of this analog switch appears at pin15 of U15:D and is labeled V_(SW) in FIG. 8.

[0083] The state transition threshold voltage V_(TH), is generated atoutput pin 1 of operational amplifier U14:A. Assuming an idealoperational amplifier U14:A, it is readily shown that the output signalV_(TH) is related to signal V_(OB) and the signal V_(SW) by:

V _(TH)=2V_(o) _(—) _(B) −V _(SW)  (Eqn. 2)

[0084] The instantaneous value of the signal V_(SW) is dependent uponthe logic state of the switch control input (pin 16) of U15:D. When thesignal at switch control input (pin 16) of analog switch U15:D is in alogic “0” state, V_(SW) follows signal V_(OA), generated by DAC U13 andconnected to input terminal pin 14 of U15:D. When the control signal atswitch control input (pin 16) of analog switch U15:D is in a logic “1”state, the circuitry driving output terminal, pin 15, of analog switchU15:D is placed in a very high impedance state and V_(SW) closelyfollows V_(OB) by virtue of the low resistance value of resistor R30 andthe extremely small input bias current of operational amplifier U14.

[0085] The signal communicated to the switch control input of U15:D isprovided by a logic OR gate U16:A. The input signals to OR gate U16:Aare a hysteresis-enabling control output from DSPC 630 (\HYSEN) and thesignal from the output of analog comparator U12:A, (pin 12). The logicstate of signal \HYSEN is generated under DSP software control and ismaintained in the logic “0” state under normal operation. The signal\HYSEN is set to a logic “1” state only during certain manufacturingsystem calibration and test procedures to isolate the hysteresisgenerating signal V_(OA) from V_(SW).

[0086] As discussed earlier, the value of V_(SW) and hence V_(TH) ismodal by virtue of the state of analog switch U15:D, which is dependentupon the state of digital signal \ARC at output terminal of analogcomparator U12:A (pin 12). The relation between the signals V_(OA) andV_(OB), both developed by DAC U13 and comparator threshold valuesV_(THNA) and V_(THAN) will now be derived. Assume first that the outputsignal of analog comparator U12:A is initially in a logic high state.This requires the level shifted chamber voltage signal, V_(CS) on pin 4of U12:A, to be at a higher level than the present threshold voltage,V_(TH) on pin 5 of U12:A; by definition the NON_ARCING state. In saidscenario, the output terminal of analog switch U15:D presents a highimpedance and as discussed previously V_(SW) is forced to take the valueV_(OB) by virtue of the low resistance value of R30 and the low inputbias current of operational amplifier U14:A Under this condition, thesignal at the output terminal of op amp U14:A follows V_(OB), and fromEqn. 2, V_(TH) also takes the value V_(OB). Thus, voltage signal V_(OB)directly sets the scaled, level shifted voltage at which comparatorU12:A transitions from the NON_ARCING to the ARCING state, V_(THNA)according to:

V_(THNA)=V_(OB)  (Eqn. 3)

[0087] Once the scaled, shifted chamber voltage magnitude, V_(CS), dropsbelow the programmed NON_ARCING to ARCING state transition value ofthreshold voltage V_(TH), V_(THNA), generated according to Eqn 3, thesignal at the output of comparator U12:A transitions from a logic “1”state (NON_ARCING) to a logic “0” (ARCING) state. Assuming the \HYSENcontrol signal is in the logic “0” state (enabling the programmablehysteresis function), analog switch U15:D closes and the output ofanalog switch U15:D, V_(SW), follows the input of analog switch U15:D,V_(OA) asserted by DAC A of U13, as discussed above. From Eqn. 2 withV_(OB) set to V_(THNA), the resulting threshold value V_(TH) becomes:

V _(TH)=2V _(THNA) −V _(OA)  (Eqn. 4)

[0088] If the programmed value of hysteresis (scaled to reflect thegains of the PSIM and level shifting network) is V_(HYSS), then settingV_(OA) according to:

V _(OA) =V _(THNA) −V _(HYSS)  (Eqn. 5)

[0089] and substituting into Eqn. 4 provides:

V _(THAN) =V _(THNA) +V _(HYSS)  (Eqn. 6)

[0090] Setting V_(OA) according to Eqn. 5 allows the addition of a fixedhysteresis voltage value V_(HYSS) to the NON_ARCING to ARCING statetransition voltage V_(THNA) when the ADU is in the ARCING state tocreate the ARCING to NON_ARCING transition voltage value V_(THAN). Insummary, in this embodiment, DAC B output signal V_(OB) is used todirectly set the chamber voltage at which the programmable comparatortransitions from the NON_ARCING to ARCING state according to Eqn. 1,while Eqn. 5 indicates an algorithm to determine a value for DAC A toadd a hysteresis value to V_(THNA) to generate a related, but possiblyhigher transition voltage V_(THAN) from the ARCING to NON_ARCING state.

[0091] According to one implementation, the desired chamber thresholdvoltage value at which programmable comparator 620 transitions from theNON_ARCING to ARCING state and the desired voltage to be added to thischamber voltage threshold value to define the chamber voltage value atwhich the programmable comparator transitions from the ARCING toNON_ARCING state can be communicated to DSPC 630 from logic arrangement60 via local data interface 70 and DSPC 630 can compute the correctdigital values to send to DAC U13 to generate the appropriate signalsV_(OA) and V_(OB) by virtue of affine transformations using appropriatescaling and offset constants stored integral to the DSP memory. In oneexample embodiment, to provide highly accurate threshold values, saidscaling and offset constant values are computed for an individual moduleto account for the normal deviations from nominal values encountered inelectronic components (e.g., resistor tolerance values) by virtue of acalibration routine. These calibration constant values are stored in aserial EEPROM integral to DSPC 630.

[0092] According to one example implementation, the sample rate of theanalog to digital converters of DSP 630 is on the order of 10 kHz perchannel, or one complete sample of the filtered chamber voltage andcurrent signals, V_(CH) and I_(CH) every 100 uS. At this rate, arandomly occurring microarc of duration of 1 uS or less has a less than1% probability of being detected by the DSP and, as discussed above,microarcs on the order of 1 uS are both common and can cause damage inintegrated circuit manufacture. To reliably detect microarcs on theorder of 1 uS or less in duration, ADU 50 includes high speed arcdetector logic unit (ADLU) 640 that co-functions with the ProgrammableThreshold Comparator 620 and which can be controlled and monitored byDSPC 630 to generate statistical data regarding arcing during the PVDprocess. Referring to FIG. 6, DSPC 630 provides control signals andsystem clock signal SYSCLK 650 to ADLU 640 and reads and writes data toand from ADLU 640 in a manner to be discussed subsequently. ADLU 640includes a first high-speed counter adapted to count the number of timesthe \ARC signal transitions from a NON_ARCING logic state to an ARCINGlogic state as determined by the programmed voltage threshold value ofProgrammable Threshold Comparator 620 and the voltage between anode andcathode of chamber 10. As discussed previously, the duration of an arcis one indication of its severity, along with the magnitude of voltagedepression and current increase. Accordingly, ADLU 640 also includes atimer adapted to measure the duration over which the ProgrammableThreshold Comparator spends in the ARCING state since the last timerreset set in a manner to be discussed subsequently. According to oneexample implementation, the timer is a counter tabulating clock signalcycles. According to one particular example implementation, the fixedclock operates at 30 MHz. The counter accumulates a (count) valueproportional to the total time (since last reset) the chamber has beenin an arcing condition during the production cycle. Maintaining arunning count of the number of system clock cycles that have occurredduring the ARCING state provides one measure as to the total time thesputtering process has spent in an arcing condition.

[0093] According to one specific example, the ADLU includes interfacemeans to DSPC 630 in the form of an address and data bus and acceptscontrol signals from DSPC 630 such that DSPC 630 may read and write datafrom the device. The ADLU includes a register that permits DSPC 30 tocontrol certain ADLU functions, such as resetting, enabling anddisabling of counters, and also includes additional registers andcontrol logic to permit DSPC 630 to read status information from theADLU.

[0094]FIG. 9 illustrates one example implementation of ADLU 640 of thepresent invention using a general purpose field programmable logic array(FPLA), programmed utilizing well-known FPLA design tools. Signals shownexternal to ADLU 640 in FIG. 9 represent signals present on physicalpins of the FPLA, the signals being either pre-assigned to particularpins of the FPLA during fabrication of the FPLA, or defined by the FPLA“program” downloaded to the FPLA by the DSP on power-up using anintegrated FPLA Program Interface 910 pre-defined at fabrication. ADLU640 comprises a Counter Unit (CU) 920, a Counter Control Register (CCR)930, and a Counter Status Buffer (CSB) 940 coupled by an Internal DataBus structure 950 to a DSP Interface Logic Arrangement 960. Signal \ARC622 is a logical input to ADLU generated by Programmable ThresholdComparator 620 as discussed previously. The system clock signal, SYSCLK650 is a 30 MHz. logic square wave signal provided by DSPC 630 andprovides the time base for the ADLU.

[0095]FIG. 10 illustrates one example implementation of CU 920 of thepresent invention. CU 920 comprises a 16-bit asynchronous binary counter(ACC) 1010, a 32-bit asynchronous binary counter (ATC) 1020, three16-bit latches (ACC Latch 1030, ATC High Latch 1040, and ATC Low Latch1050), and three 16-bit tri-state buffers (ACC 3-State Buffer 1060, ATCHigh 3-State Buffer 1070, and ATC Low 3-State Buffer 1080). Threedigital signals, counter reset (CRST), enable (ENB) and snapshot (SNP)are provided from Counter Control Register 930 to control the operationof the ACC and the ATC counters respectively. When asserted by CCR 930,the CRST signal causes both the ACC and ATC counters to reset to zeroand holds the counters in the reset condition while asserted. When CCR930 releases the CRST signal, the counters are respectively enabled, andincrement on each high-to-low transition of their respective clock (CLK)signal inputs. Each counter has a respective overflow bit (OVF) which isasserted (and latched) should a particular counter “roll over” bycounting past its maximum quantity capacity and back to zero. An OVFsignal remains high until cleared by assertion of the CRST signal. ACCcounter 1010 is driven by signal ACCLK, ACCLK being derived from theoutput terminal 1092 of D flip-flop 1090. ATC counter 1020 is driven bysignal ATCLK, which in turn originates from the output terminal of NANDgate 1094.

[0096]FIG. 11 is a timing diagram illustrating the relationships betweenvarious signals of ADLU 640. Referring to FIGS. 10 and 11, the DSPCsystem clock signal, SYSCLK 650 is negated by inverter 1096 to become\SYSCLK 1120. Signal \SYSCLK drives the clock input terminal 1091 of Dflip-flop 1090. On each high-to-low transition of the SYSCLK signal fromthe DSP, the value appearing at the D input terminal 1093 is latchedinto the D flip-flop and appears at the Q output terminal 1092 offlip-flop 1090 after a short propagation delay.

[0097] The signal presented at the D input terminal 1093 of the Dflip-flop is driven by AND gate 1098. Input signals to AND 1098 are thesignal ENB 1130 provided from the Counter Control Register 930, and thenegation of signal \ARC 622 (\\ARC 1150) from inverter 1097, signal \ARC622 being provided by Programmable Comparator 620. When either thesignal ENB 1130 is in the logic low (FALSE) state, or the \ARC signal isin the high state (indicating detection of a NON_ARCING chambercondition), the signal at the D input terminal 1093 is in the logic lowstate. Conversely, when the ENB signal is in the logic high state(thereby enabling counting), and the \ARC signal is in the logic lowstate (indicating detection of an ARCING chamber condition), the signalat the D input terminal 1093 is in the logic high state. Therefore,assuming counting is enabled (signal ENB 1130 is in a logic high state),the ACCLK signal 1160 will be in the logic low state on subsequenthigh-to-low transitions of the SYSCLK when the chamber is detected in aNON_ARCING condition. When an ARCING condition is detected, for exampleas indicated at 1180 in FIG. 11 (and assuming counting is stillenabled), the \ARC signal is asserted low. On the next high-to-lowtransition of the SYSCLK signal (as indicated at 1182 in FIG. 11), theACCLK signal will transition from a low to a high logic state, andremain in a high logic state through subsequent cycles of the SYSCLKsignal, until the ARCING condition is no longer detected (and the \ARCsignal returns to a logic high state as indicated at 1184 in FIG. 11).

[0098] ACC counter 1010 increments at each low-to-high transition of thesignal at its CLK input terminal whenever the CRST signal is assertedlow. Thereby, ACC counter 1010 effectively counts the quantity ofchamber transitions from the NON_ARCING condition to the ARCINGcondition, while the ENB signal is asserted high (enabling thecounting). In the example embodiment, ACC counter 1010 can resolvemicroarcs detected by the Programmable Comparator 620 (generating the\ARC signal) as short as 33 nS using a SYSCLK signal having a frequencyon the order of 30 MHz. Higher resolution can be achieved by increasingthe clock rate.

[0099] ATC counter 1020 is used to estimate the total time the chamberis in the ARCING condition as determined by Programmable Comparator 620.ATC counter 1020 increments at each low-to-high transition of the signalat its CLK input terminal whenever the CRST signal is asserted low. TheCLK input terminal of ATC counter 1020 is driven by signal ATCLK 1170provided by AND gate 1094 having ACCLK and SYSCLK signal inputs. SignalATCLK 1170 begins tracking the SYSCLK signal 1110 whenever counting isenabled (ENB signal 1130 is high) and a chamber ARCING condition isdetected (\ARC signal 1140 is low), for example at 1186 in FIG. 11.Thereafter, ATC counter 1020 counts the clock cycles of the ATCLK signal1170 that persist while the Programmable Threshold Comparator is in theARCING state, indicating an arc in the PVD chamber. Using a 30 MHzsystem clock, the duration of each ARCING condition can be resolved towithin a 33 nS increment.

[0100] The ACC 1030, ATC High 1040 and ATC Low 1050 latching snapshotregisters permit the ACC counter 1010 value, the ATC counter 1020 highorder word, and the ATC counter 1020 low order word values to becaptured respectively, on command at an instant in time. This permitsDSPC 630 to read the state of the counters at a specified instant,holding those values for subsequent retrieval by DSPC 630, whilepermitting the ACC and ATC counter to continue to operate according totheir respective logic described above. Each of these three 16-bitregisters is arranged and configured to capture the instantaneouscorresponding counter value on a low-to-high transition of the SNPsignal, provided by Counter Control Register 930 under control of DSPC630 as will be discussed. The output signal of each of the snapshotregisters are 3-state buffered to an internal data bus 950 by the ACC1060, ATC High 1070 and ATC Low 1080 3-state buffers respectively. TheDSP Interface Logic 960 asserts an enable signal on RACC 1086 to ACC3-state buffer 1060 in order to provide the captured value of ACClatching snapshot register 1030 on internal bus 950; asserts an enablesignal on RATH 1087 to ATC High 3-state buffer 1070 in order to providethe captured value of ATC High latching snapshot register 1040 oninternal bus 950; and asserts an enable signal on RATL 1088 to ATC Low3-state buffer 1080 in order to provide the captured value of ATC Lowlatching snapshot register 1050 on internal bus 950.

[0101] Referring again to FIG. 9, the CCR latching register 930generates the SNP, CRST and ENB signals. DSP Interface Logic 960provides proper address decoding and timing signals, asserting thecommanded values of the SNP, CRST and ENB signals on Internal Data Bus950 and generating signal WCCR to latch these values into the CCR whencommanded to do so by DSPC 630. Counter Status Buffer (CSB) 940 is a3-state buffer arranged and configured to assert present values of theCRST, ENB, ACCLK, COVF and TOVF signals onto internal data bus 950 whencommanded by DSP Interface Logic 960 through assertion of the signalRCSB. DSP Interface Logic 960 subsequently asserts these signals ontothe DSPC data bus for use by DSPC 630.

[0102] Referring again to FIG. 9, externally supplied signals in theform of data bus lines DB0-DB15 provide bi directional communication ofdata to and from DSPC 630, according to the actions of signals \STRB,W/R and address lines AD0-AD15, asserted by DSP 630 to facilitatecommunication with external devices such as ADLU 640. These data linesare effectively tied internally directly to internal data bus 950 ofADLU 640. DSP 630 asserts the \STRB signal low when attempting tocommunicate with any external peripheral device, such as ADLU 640. DSPC630 also asserts signal W/R low when attempting to read from a device,and high when attempting to write to a device. These are general purposesignals asserted by DSPC 630 to communicate with any device. The signal\ADLU_CS is asserted low by DSPC 630 specifically to read or write datafrom or to ADLU 640. DSP Interface Logic 960 is included in ADLU 640 togenerate timing and control signals WCCR, RCSB, RACC, RATL and RATH oncommand by DSPC 630, according to the operation of the control signals\STRB, W/R and a decoding of address signals AD0 and AD1. Signal WCCR isused to latch the values of ENB, CRST and SNP asserted by DSPC 630 ontoInternal Data Bus 950 into CCR 930. Signal RCSB causes the values in CSB940 to be asserted onto the Internal Data Bus to be subsequently read byDSPC 630. Signals RACC, RATL and RATH enable ACC 3-State Buffer 1060,ATC High 3-State Buffer 1080 and ATC Low 3-State Buffer 1070respectively as described above to assert the values in latches ACCLATCH 1030, ATC LOW LATCH 1050 and ATC HIGH LATCH 1040 onto InternalData Bus 950 to be subsequently read by DSPC 630.

[0103]FIG. 12 illustrates one example implementation of DSP InterfaceLogic 960 of the ADLU 640 of the present invention, to generate signalsWCCR, RCSB, RACC, RATL and RATH shown in FIG. 9. Internal to DSPInterface Logic 960, control logic unit (CLU) 1210 inverts the \STRBsignal, asserted by DSP 630, via inverter 1220 to form the internalsignal \\STRB. Signal \\STRB is a logic high when DSPC 630 is attemptingto communicate with any external device. The WR signal is provided atthe output of AND gate 1230, from input signals \\STRB and the signalW/R, which is asserted high by DSPC 630 when attempting to write to anexternal device. The W\R signal is inverted via inverter 1240 to formsignal \W/R, with signal \W/R asserted a logic high when the DSPInterface Logic 960 is attempting to read from any external device. TheRD signal provided at the output of AND gate 1250 from input signals\\STRB and \W/R, is consequently asserted high whenever the DSPC 630 isreading from an external device.

[0104] Address decoding to generate the control signals for ADLU 640 isfunctionally provided by an address decoder, for example, a 2-to-4binary address decoder 1260 as shown in FIG. 12. As stated above, DSPC630 asserts logic 0 on the \ADLU_CS terminal of ADLU 640 when readingfrom or writing to ADLU 640. When the \ADLU_CS signal is set to a logichigh state, all four signals at output terminals of decoder 1260, Q0, .. . , Q3 are set to a logic low state. When the \ADLU_CS signal isasserted in a logic low state by DSPC 630, decoder 1260 sets exactly oneof the signals at the output terminals to a logic high state, theparticular output set to logic high determined from the present value ofthe A0 and A1 bits asserted by DSPC 630 and in accordance with Table 1,where “0” in Table 1 is a logic low, “1” is a logic high, and “X” is anirrelevant state: TABLE 1 Output Input Input Input Output \ADLU_CS A1 A0Asserted High 1 X X NONE 0 0 0 Q0 0 0 1 Q1 0 1 0 Q2 0 1 1 Q3

[0105] With the decoder logic as set forth above, Table 2 defines thelogic generating the signals at each of the function select outputs inFIG. 12, as well as the operation performed by DSPC 630 on the ADLU.TABLE 2 SIGNAL NAME LOGIC DSPC 630 FUNCTION WCCR Q0 AND WR WRITE COUNTERCONTROL REGISTER VALUE RCSB Q0 AND RD READ COUNTER STATUS BUFFER RACC Q1AND RD READ ACC LATCH VALUE RATL Q2 AND RD READ ATC LOW LATCH VALUE RATHQ3 AND RD READ ATC HIGH LATCH VALUE

[0106] The processing of signals I_(CH) and V_(CH) generated by AnalogSignal Conditioner 610 is now discussed in greater detail. Referringagain to FIG. 6, the signals I_(CH) and V_(CH), generated by AnalogSignal Conditioner 610 are responsive to the chamber voltage andcurrent, but are conditioned by Analog Signal Conditioner 610 tominimize aliasing at sampling frequencies greater than about 10 kHz.Integral to the TMS320F2407 DSP incorporated in DSPC 630 is a 16channel, dual 10 bit analog to digital converter module that convertsvoltages at its input channels into numbers ranging between 0 and 1023,in proportion to a reference voltage, and an internal timing mechanismunder software control that can sample the up to 16 input voltages at afixed rate. In one particular embodiment, the reference voltage for theinternal analog to digital converter is provided by a commerciallyavailable bandgap regulator, Model REF193, manufactured by NationalSemiconductor. This regulator provides a stable, accurate 3.00 voltsource to the analog to digital converters. Thus, the integral analog todigital converters provided in the digital signal processor of DSPC 630convert the time varying signals I_(CH)(t) and V_(CH)(t) to numbersequences {N_(ICH)} and {N_(VCH)} ranging between 0 and 1023 accordingto:

N _(ICH)(n)=FIX((I _(CH)(nT)/V _(REF))*1024)  Eqn 8

and

N _(VCH)(n)=FIX((V _(CH)(nT)/V _(REF))*1024)  Eqn 8

[0107] Where the function FIX(arg) truncates the value of its argument“arg” to the nearest integer, n denotes the nth sample taken by DSPC 630from a reference time and T is the sample period. In one particularembodiment, the DSP is programmed to convert the analog signals V_(CH)and I_(CH) at a rate of 10 kHz, resulting in sampled data sequences ofnumbers {N_(VCH)} and {N_(ICH)} responsive to the chamber voltage andcurrent. In one particular embodiment, software internal to the DSPprovides for the application of user selectable digital finite impulseresponse (FIR) filters to the sequences, resulting in filtered sequences{F_(VCH)} and {F_(ICH)} respectively, although other signal processingtechniques can be applied to the sequences without loss of generality.In one particular embodiment, an affine transformation is applied to thesequences {F_(VCH)} and {F_(ICH)} resulting in sequences of numbers{SF_(VCH)} and {SF_(ICH)} that are a scaled integer estimate sequencesof the chamber voltage and current. In one example, the affinetransformations are such that a continuously applied chamber voltage of1000 volts results in the generation of a sequence of integers each withvalue 1000, with other voltage values scaled proportional. Similarly, inthis example, the affine transformation applied to the sequence derivedby sampling and converting the I_(CH) signal takes into considerationthe various gains and offsets of the PSIM and Analog Signal Conditioningcircuits, resulting in a transformation in which a current of 10.00Amperes appears as the integer 1000, with other values proportional.

[0108] In one example implementation, the present value of the sequencesare communicated via high speed communication interface 70 to logicarrangement 60 where logic arrangement 60 uses the present and pastvalues to compute an adaptive arc threshold voltage value to be used byProgrammable Threshold Comparator 620. This adaptive arc thresholdvoltage value and desired hysteresis level is subsequently communicatedfrom logic arrangement 60 back to DSPC 630 via High Speed CommunicationInterface 70. DSPC 630 then converts the desired threshold values to theappropriate DAC values according to the operation of ProgrammableThreshold Comparator 620. This approach results in a near real timeadaptive threshold. In another example implementation, the algorithms togenerate the adaptive threshold reside in DSPC 630 itself, resulting inan adaptive voltage threshold with minimal delay.

[0109] One example algorithm to generate an adaptive arc voltagethreshold is to base the computed threshold on a moving average of thevoltage sequence computed by DSPC 630, the length of the moving averagechosen to be long compared to the expected duration of an arc, but shortwith respect to the period of rotation of the steering magnet. At a 10kHz sample rate, the moving average can be computed using a uniformlyweighted 64 point FIR filter, the sequence at the filter outputrepresenting the average of the previous 6.4 mS of voltage measurements.In one implementation, the adaptive arc threshold value is computed bysubtracting a fixed voltage from the moving average. In another exampleimplementation, the adaptive threshold is computed as a fixed percentageof the moving average.

[0110] These filtered, transformed sequences can also be used to providefurther information indicative of the overall health of the process. Inone example, multiplying the instantaneous value of the current sequencewith the instantaneous value of the voltage sequence provides aninstantaneous power sequence that can be used to verify that the actualpower delivered to the vacuum chamber is that delivered by the powersupply. Such a sequence can be used to determine, for example, that acable breakdown is occurring, shunting current around the vacuumchamber. Another example of the use of these sequences is that they canbe used as an independent means to estimate the rotational speed of thesteering magnet. As described above, it has been observed that thechamber voltage and current vary periodically with the steering magnetperiod as the chamber impedance varies due to geometric and otherconsiderations. In one example, the scaled voltage or current sequenceis passed through a digital high pass filter to remove the DC component.The resulting AC sequence is then tracked by a digital phase lockedloop, from which the rotational frequency of the steering magnet isestimated. In another example implementation, a discrete Fouriertransform is applied to the voltage or current sequence, and the magnetrotation frequency determined from the resulting spectrum. If theestimated rotation speed differs significantly from the expectedrotation speed, a mechanical or electrical problem may be the cause.This information can be used to detect an incipient fault in themechanical or electrical system.

[0111] According to another example embodiment of the present invention,the components and operation described above are replicated formonitoring multiple chambers or for detecting ARCING based uponadditional threshold values applied to a single chamber voltage andcurrent signals. In a particular example embodiment, four independentlyoperating ADU functions controlled by a single DSPC 630 are provided.The four chamber version of the ADU can be configured to simultaneouslymonitor four independent chambers via four PSIMs, or a single PSIM candrive multiple ADU chamber inputs by wiring the corresponding VPSIM+,VPSIM−, IPSIM+ and IPSIM− ADU input signals for multiple chambers inparallel. In an example embodiment, when all four ADU functions aremonitoring a single chamber via a single PSIM and wired in this manner,four different threshold values can be programmed for a single chamber.A count of number of arcs and arc duration at each programmed thresholdvalue is maintained by the combination of corresponding ProgrammableComparator 620 and ADLU 640. In the embodiment, DSPC 630 has access toall four ADLU functions, and arcing conditions can be resolved into oneof four levels corresponding to the four independently programmedthresholds.

[0112] For instance, in a system employing four independent monitorsattached to a single PSIM per above, and voltage threshold magnitudesprogrammed at 100, 200, 300 and 400 volts, a single arc having a minimumvoltage magnitude of 250 volts will appear on the monitors withthresholds programmed at 300 and 400 volts, but not on those programmedat 100 and 200 volts. Furthermore, if the system is capturing a singlearc in this manner, the period over which the chamber voltage collapsesbelow the 300 volt level will appear simultaneously in the ADLU arc timecounters corresponding to the 300 and 400 volt level, while the periodover which the chamber voltage collapse is between 300 and 400 voltswill appear only on the ADLU arc time counter corresponding to the 400volt level. The arc event can then be resolved into two arc times—thearc time spent between 200 and 300 volts, read directly from the arctime counter of the ADLU corresponding to the 300 volt threshold, plusthe arc time spent between 300 and 400 volts, computed by taking thedifference between the ADLU arc time counters corresponding to the 400volts and 300 volts respectively. This algorithm can be repeated asrequired for other arcs of different intensities.

[0113] In one particular example implementation, DSPC 630 samples thefour ADLU register sets at a 10 kHz rate and communicates the arc countand arc time count for all four channels via High Speed CommunicationInterface 70 to Logic Arrangement 60. DSPC 630 also samples andtransfers the nominal, filtered chamber current ICH, and filteredchamber voltage V_(CH) to Logic Arrangement 60, which performs themathematical operations required to resolve the arc per above andcompute an estimate of arc energy. All four arc voltage threshold valuescan be computed adaptively by extension of the discussion above. Inanother example embodiment, DSPC 630 performs the computationsinternally, transmitting the resulting estimate of arc relatedparameters, such as arc time at each threshold value, and estimated arcenergy to Logic Arrangement 60.

[0114] According to one example implementation, the logic arrangement 60is an external logic arrangement, for example a programmable logiccontroller (PLC), tophat, or similar computing device. According to amore particular embodiment, the logic arrangement 60 is a SchneiderAutomation M1-E PLC. According to one aspect of the present invention,the ADU is incorporated into a Momentum form factor and adapted tocommunicate with Momentum tophats and programmable logic controllers(PLCs).

[0115] In one implementation, the data collected by the logicarrangement 60 is recorded. Software running on the logic arrangement 60logs data, graphs data, and can provide network-based alarms responsiveto the data. A system controller provides real-time control of theplasma generation application. When the arc count and/or arcing durationexceeds a selected quantity per deposition, the logic arrangement 60determines according to a pre-defined algorithm that the arcing isdamaging the substrate during material deposition, and communicates withthe system controller to terminate the deposition. The logic arrangement60 can also indicate that the substrate being processed will havereduced yield due to the arcing.

[0116] In addition to counting arcs and the cumulative duration ofarcing for each deposition, the logic arrangement 60 is used to performother real-time analysis of arc information in other implementations.For instance, analysis such as recording the total number (and duration)of arcs for the target, recording the arc intensity (referring to theproximity to ground potential, indicative of a direct short), anddetecting continual arcing, which indicates a potential defect in thetarget requiring complete tool shut down for repair. In anotherimplementation, a system controller provides a signal based on arcingrates, on arcing durations, on rate of change of arc rate/durations, orbased on arc “quality,” arc quality being proportional to duration,quantity and arc intensity (i.e., magnitude) or severity (as measure forexample, by a product of the arc duration and magnitude).

[0117] According to another example embodiment of the present invention,a method integrates an arc detector with hardware necessary to inform auser, in real-time, that there is a problem with the sputtering sourceand that the newly-processed wafer may have reduced yield. Accordingly,various embodiments of the present invention can be realized to providearc detection in other plasma generation control applications, such asfor case hardening steel, among others. Generally, the circuitarrangements and methods of the present invention are applicablewherever a plasma generation chamber or its equivalent might beimplemented.

[0118] The various embodiments described above are provided by way ofillustration only and should not be construed to limit the invention.Based on the above discussion and illustrations, those skilled in theart will readily recognize that various modifications and changes may bemade to the present invention without strictly following the exemplaryembodiments and applications illustrated and described herein. Suchmodifications and changes do not depart from the true spirit and scopeof the present invention that is set forth in the following claims.

What is claimed is:
 1. A plasma generation apparatus, comprising: apower supply circuit having a cathode enclosed in a chamber, and adaptedto generate a power-related parameter; and an arc detection arrangementcommunicatively coupled to the power supply circuit and adapted toassess the severity of arcing in the chamber by comparing thepower-related parameter to at least one threshold.
 2. The apparatus ofclaim 1, wherein the arc detection arrangement is further adapted tomeasure arcing duration responsive to comparing the power-relatedparameter to the at least one threshold.
 3. The apparatus of claim 1,wherein the arc detection arrangement is further adapted to measurecumulative arcing duration responsive to comparing the power-relatedparameter to at least one threshold.
 4. The apparatus of claim 1,wherein the arc detection arrangement is further adapted to measurearcing intensity responsive to comparing the power-related parameter toat least one threshold.
 5. The apparatus of claim 4, wherein the arcdetection arrangement is further adapted to measure arcing durationresponsive to comparing the power-related parameter to at least onethreshold.
 6. The apparatus of claim 5, wherein the arc detectionarrangement is further adapted to measure arcing energy responsive tocomparing the power-related parameter to at least one threshold.
 7. Theapparatus of claim 5, wherein the arc detection arrangement is furtheradapted to measure cumulative arcing energy responsive to comparing thepower-related parameter to at least one threshold.
 8. The apparatus ofclaim 1, wherein the arc detection arrangement is further adapted toassess the severity of arcing as a function of a product of arcingintensity and arcing duration.
 9. The apparatus of claim 1, wherein thearc detection arrangement is further adapted to assess the severity ofarcing as a function of a sum of products of arcing intensity and arcingduration.
 10. The apparatus of claim 1, wherein at least one thresholdis programmable via a logic arrangement coupled to the arc detectionarrangement.
 11. The apparatus of claim 1, wherein at least onethreshold is programmable responsive to a non-arcing value of thepower-related parameter.
 12. The apparatus of claim 1, wherein the arcdetection arrangement is adapted to digitize the power-related parameterbefore comparing to the at least one threshold.
 13. The apparatus ofclaim 1, further comprising a logic arrangement communicatively coupledto the arc detection arrangement, and adapted to process digitalinformation representative of arcing transmitted from the arc detectionarrangement.
 14. The apparatus of claim 13, wherein the logicarrangement is a programmable logic controller.
 15. An apparatus forassess arcing severity in a plasma generation chamber, comprising: meansfor determining arc intensity by comparing a power-related parameter toat least one arc intensity threshold; means for timing an arc durationresponsive to comparing the power-related parameter to the at least onearc intensity threshold; means for computing arc energy as a function ofarc intensity and arc duration; and means for adding the arc energy toan accumulated arcing energy.